System and method for generating cyclic codes for error control in digital communications

ABSTRACT

A K-bit information signal represented by a polynomial U(x) having a degree K−1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G 1 (x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P−1. T(x) equals U(x)G 1 (x). An initial cyclic code represented by a polynomial R 1 (x) is generated for the transformed information signal using a second transform represented by a polynomial G 2 (x), where G 2 (x) has high-order leading-zero terms. R 1 (x) equals the remainder obtained by dividing T(x) by G 2 (x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R 2 (x) using the first transform. R 2 (x) equals R 1 (x)/G 1 (x).

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No.10/055,910, filed Jan. 28, 2002, which in incorporated by referenceherein in its entirety.

FIELD OF THE INVENTION

The present invention relates to digital communications. Moreparticularly, the present invention relates to cyclic codes for errorcontrol in digital communications.

BACKGROUND OF THE INVENTION

Communicating information via the internet and other digitalcommunications systems has become common in the United States andelsewhere. As the number of people using these communications systemshas increased, so has the need for transmitting digital data at everincreasing rates.

Information transmitted by a digital communications system is typicallyencoded and transmitted as a series of information code words. Encodingis used to improve the overall performance of a digital communicationssystem. In addition to encoding information prior to transmission, manydigital communications systems also calculate groups of bits or codewords that are appended to a group of information bits prior totransmission. These bits or code words may be used by a signal decoderof a receiver to detect and/or correct bit errors that can occur duringtransmission. Cyclic Redundancy Check (CRC) bits are an example of bitsappended to a group of information bits prior to transmission. Thesebits are used by a signal decoder to detect and/or correct bit errors.

Typically, the bits and/or code words appended to a group of informationbits for transmission form part of a cyclic code or a systematic cycliccode. Cyclic codes or more particularly systematic cyclic codes areoften generated using a linear feedback shift register (LFSR) designedto implement a particular generator polynomial or a particular paritypolynomial. The generation of a systematic cyclic code typicallyinvolves three operations. These operations are: (1) multiplying aninformation signal, U(x), by X^(n-k); (2) dividing the productU(x)·X^(n-k) by a generator polynomial G(x) to obtain a remainder R(x);and (3) adding R(x) to U(x)·X^(n-k).

Systems and methods for generating cyclic codes exist. Theseconventional systems and methods, however, have limitations that preventthem from operating at high data rates. In particular, the nestedfeedback loops of the LFSR used to generate the code words form a speedbottleneck.

Conventional techniques such as look-ahead, pipelining, and parallelismare often used to overcome speed bottlenecks in digital communicationssystems. These conventional techniques, however, cannot always beapplied successfully to design digital communications systems that willoperate at a data rate in excess of 2 Gb/s. Applying these conventionaltechniques is particularly difficult, for example, when dealing withnested feedback loops such as the feedback loops of a linear feedbackshift register used to generate the code words of a cyclic code.

There are several approaches, for example, that can be used in applyinglook-ahead in the context of a circuit having nested feedback loops.Many of these approaches will not, however, improve the performance ofthe digital circuit to which they are applied, and some of theseapproaches can even degrade circuit performance or improve theperformance in a less-than-linear manner with respect to look-aheadfactor. This is due at least in part because look-ahead networks mayincrease the iteration bound of a circuit. In similar fashion, theapplication of conventional pipelining and parallelism techniques tonested feedback loops in high speed digital communications systems willnot necessarily result in improved performance. Applying theseconventional techniques leads to fan-out problems in a high speeddigital communications system, and thus they cannot be used to overcomespeed bottlenecks caused by nested feedback loops in a high speeddigital communications system.

There is a current need for new design techniques and digital logiccircuits that can be used to build high-speed digital communicationsystems. In particular, there is a current need for new systems andmethods for generating cyclic codes for error control in digitalcommunication systems that do not create speed bottlenecks and preventdigital communications systems from operating at high data rates.

BRIEF SUMMARY OF THE INVENTION

Systems and methods for generating cyclic codes for error control indigital communications are presented. Generally speaking, the inventionoperates by receiving an initial group of information bits to betransmitted. This initial group of information bits is operated on toform a transformed group of bits. The transformed group of bits isfurther operated on to form an initial codeword. This initial codewordis then transformed to form a codeword of a conventional cyclic code andappended to the initial group of information bits.

In an embodiment of the invention, a K-bit information signalrepresented by a polynomial U(x) having a degree K−1 is received. Theinformation signal is operated on to form a transformed informationsignal using a first transform represented by a polynomial G₁(x) havinga degree P. The transformed information signal is represented by apolynomial T(x) having a degree K+P−1. T(x) equals U(x)G₁(x). An initialcyclic code represented by a polynomial R₁(x) is generated for thetransformed information signal using a second transform represented by apolynomial G₂(x). The second transform, G₂(x), has high-orderleading-zero terms. R₁(x) equals the remainder obtained by dividing T(x)by G₂(x). The initial cyclic code is transformed to form a final cycliccode represented by a polynomial R₂(x) using the first transform. R₂(x)equals R₁(x)/G₁(x).

The invention can be used to generate the code words of conventionalcyclic codes and/or systematic cyclic codes. For example, in anembodiment, the final cyclic code generated is a cyclic redundancy checkcode. In another embodiment, the final cyclic code generated is aBose-Chaudhuri-Hocquenghem code. In still another embodiment, the finalcyclic code generated is a Reed-Solomon code. The invention can also beused, for example, to generate cyclic Hamming codes, cyclic Golay codes,and maximum-length shift-register codes.

In an embodiment, the transformed information signal is formed by addingthe information signal, U(x), to at least one time-shifted copy of theinformation signal, U(x+t).

In an embodiment, a first linear feedback shift register is used to formthe initial cyclic code and a second linear feedback shift register isused to form the final cyclic code. The final cyclic code is formed bydividing the initial cyclic code, R₁(x), by the first transform, G₁(x).

In an embodiment, the K-bits of the information signal, U(x), areprocessed in parallel to generate the polynomial, T(x), the initialcyclic code, R₁(x), and the final codeword bits.

Further features and advantages of the present invention, as well as thestructure and operation of various embodiments of the present invention,are described in detail below with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

Embodiments of the present invention are described with reference to theaccompanying figures. In the figures, like reference numbers indicateidentical or functionally similar elements. Additionally, the leftmostdigit of a reference number identifies the figure in which the referencenumber first appears. The accompanying figures, which are incorporatedherein and form part of the specification, illustrate the presentinvention and, together with the description, further serve to explainthe principles of the invention and to enable a person skilled in therelevant art to make and use the invention.

FIG. 1 is a block diagram of an example linear feedback shift-registercircuit for generating a cyclic code.

FIG. 2 is a block diagram of an example two parallel paths circuit forgenerating a cyclic code, which is obtained by unfolding the circuit ofFIG. 1 by a factor of two.

FIG. 3 is a block diagram of an example three parallel paths circuit,which is obtained by unfolding the circuit of FIG. 1 by a factor ofthree.

FIG. 4 is a block diagram of an example circuit that is obtained byadding an additional time delay to the innermost nested loop of thecircuit of FIG. 1 in accordance with the invention.

FIG. 5 is a block diagram of an example three parallel paths circuit,which is obtained by unfolding the circuit of FIG. 4 by a factor ofthree in accordance with the invention.

FIG. 6A is a block diagram of an example encoder according to theinvention for generating a cyclic code.

FIG. 6B is a block diagram of an example three parallel paths circuitaccording to the invention, which is obtained by unfolding the circuitof FIG. 6A by a factor of three.

FIG. 7 is a block diagram of an example encoder according to theinvention for generating a cyclic code.

FIG. 8 is a block diagram of an example linear feedback shift-registercircuit for generating a cyclic code.

FIG. 9 is a block diagram of an example linear feedback shift-registercircuit for generating a cyclic code, which is obtained by retiming thecircuit of FIG. 4.

FIG. 10 is a block diagram of an example three parallel paths circuit,which is obtained by unfolding the circuit of FIG. 9 by a factor ofthree in accordance with the invention.

FIG. 11 is a flowchart of the steps of a method according to theinvention for generating cyclic codes.

DETAILED DESCRIPTION OF THE INVENTION

Modern digital communications systems contain circuits that generatecyclic codes. Generally speaking, cyclic codes are code words (groups ofbits), interspersed between groups of information signal bits, thatpossess a large amount of structure. These code words are used, forexample, to decode bits of a received digital information signal andcorrect transmission errors. Example cyclic codes are Cyclic RedundancyCheck (CRC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, theReed-Solomon code, Cyclic Hamming codes, the Cyclic Golay code, andMaximum-Length Shift Register codes.

In the description that follows, example circuits that generate cycliccodes according to the invention and an example method for generatingcyclic codes according to the invention are described.

Example Circuits for Generating Cyclic Codes According to the Invention

FIG. 1 is a block diagram of a conventional circuit 100 that is used togenerate CRC bits. In particular, circuit 100 generates a (7, 4) cycliccode. A (7, 4) cyclic code is a code that appends a three-bit codewordto four information bits thereby forming a group of seven total bits.Circuit 100 is based on the generator polynomial G(x)=1+X+X³. G(x) hasone high-order leading-zero term (i.e., the X² term is equal to zero).

Circuit 100 includes a switch 102 and a linear feedback shift register(LFSR) 104. Switch 102 has three ports (a, b, and c). Switch 102 can beany conventional electronic switch such as, for example, anyconventional type of field effect transistors (FET). LFSR 104 has threedelay devices 106 a, 106 b, and 106 c. LFSR 104 also has two adders 108a and 108 b. Delay devices 106 can be any conventional type of delaydevice such as, for example, D-flipflops. Adders 108 represent modulo-2addition and are implemented as exclusive-or circuits. LFSR 104 has twofeedback loops. The innermost feedback loop is a nested feedback loop.This innermost nested feedback loop is formed by adders 108 a and 108 b,delay devices 106 b and 106 a, and the conductors coupling these devicestogether.

Circuit 100 has two operating modes. In a first operating mode, a groupof CRC bits or a CRC codeword (R₃, R₂, R₁) is generated by LFSR 104,wherein R₁ is output from delay device 106 a, R₂ is output from delaydevice 106 b, and R₃ is output from delay device 106 c. In a secondoperation mode, the generated CRC codeword is shifted out of LFSR 104and appended to a group of information bits.

In the first operating mode of circuit 100, the a-port of switch 102 iselectrically coupled to the b-port. In this first mode, bits of adigital information signal are input to the a-port of switch 102. Duringeach clock cycle of circuit 100, a bit of the digital information signalis output at the b-port of switch 102. This same bit is also provided toadder 108 a. The bit provided to adder 108 a is added to an output ofdelay device 106 a to form a resultant bit. This resultant bit is thenprovided as an input to adder 108 b and to delay device 106 c of LFSR104.

To better understand the first operating mode of circuit 100, considerthe following example wherein LFSR 104 is used to generate a CRCcodeword for a group of four information signal bits (1, 1, 0, 1).

Initially, each of the outputs of the delay devices 106 is a 0 bit(i.e., the codeword (R₃, R₂, R₁) of LFSR 104 is (0, 0, 0) before thefirst of four information signal bits (1, 1, 0, 1) is provided tocircuit 100). During a first clock cycle of circuit 100, the first bitof the four bits (1) is provided to the a-port of switch 102 and toadder 108 a. The 0 output bit of delay device 106 a is added to thisfirst bit (i.e., 1), using modulus-2 addition, to form an output bitequal to one (0+1=1). This output bit (1) is then provided as an inputto both delay device 106 c and adder 108 b. As a result, the output ofadder 108 b becomes 1 (0+1=1). At the start of the next clock cycle,clock cycle two, the outputs of each of the delay devices 106 arechanged to that of their inputs, and the codeword (R₃, R₂, R₁) of LFSR104 is changed from (0, 0, 0) to (1, 1, 0).

During the second clock cycle, the second bit of the four bits (1) ofthe input signal is provided to the a-port of switch 102 and to adder108 a. The 0 output bit of delay device 106 a is now added to the secondbit of the information bits (i.e., 1), using modulus-2 addition, to forma new output bit equal to one (0+1=1). This output bit (1) is thenprovided as an input to both delay device 106 c and adder 108 b. As aresult, the output of adder 106 b now becomes 0 (1+1=0). At the start ofthe next clock cycle, clock cycle three, the outputs of each of thedelay devices 106 is again changed to that of their inputs, and thecodeword (R₃, R₂, R₁) of LFSR 104 is changed from (1, 1, 0) to (1, 0,1).

In a manner similar to that described above, the codeword (R₃, R₂, R₁)of LFSR 104 is changed from (1, 0, 1) to (1, 0, 0) at the start of thefourth clock cycle and from (1, 0, 0) to (1, 0, 0) at the start of thefifth clock cycle. Thus, during the transmission of the four informationbits (1, 1, 0, 1), circuit 100 has generated a three-bit CRC codeword(1, 0, 0). This is summarized below in Table 1.

TABLE 1 Output Bits CLK Delay Device Delay Device Delay Device CycleInput Bit 106c 106b 106a 1 1 0 0 0 2 1 1 1 0 3 0 1 0 1 4 1 1 0 0 1 0 0

The settling time of circuit 100 is equal to the settling time of twoadders 108 (i.e., 2T_(adder)). This can be seen by noting that theoutput of adder 108 b is dependent on the output of adder 108 a. Asillustrated by the circuit of FIG. 3, conventional unfolding techniquescan increase this settling time of parallel CRC circuits since thecritical paths of the unfolded circuits are typically longer than thesequential ones.

In the second operating mode of circuit 100, the c-port rather than thea-port of switch 102 is electrically coupled to the b-port. In thissecond operating mode, during each clock cycle of circuit 100, a bit ofa codeword generated by LFSR 104 is output at the b-port of switch 102.Thus, by switching between the two modes of operation, circuit 100 canbe used to both generate CRC code words and append these code words togroups of bits of an information signal. For example, by switching tothe second operating mode, the codeword (1, 0, 0) calculated during thetransmission of the four information bits (1, 1, 0, 1) can be appendedto the four information bits to form seven transmission bits (1, 1, 0,1, 1, 0, 0).

As shown in FIG. 1, LFSR 104 includes two feedback loops. These feedbackloops limit the rate at which data can be processed by circuit 100.Circuit 100 cannot be clocked any faster than the settling time of theslowest feedback loop.

Unfolding is a technique for increasing the processing speed of certaindigital circuits. Unfolding involves the formation of parallelprocessing paths. However, as described herein, conventional unfoldingtechniques can cause fan-out problems and increased circuit settlingtimes. For this reason, conventional unfolding techniques cannot be usedto design high speed digital communication systems, particularly systemsintended to operate at a data rate in excess of 2 Gb/s.

FIG. 2 is a block diagram of a two parallel paths circuit 200 obtainedby unfolding the LFSR 104 of circuit 100. As shown in FIG. 2, circuit200 has four adders 202 a, 202 b, 202 c, and 202 d and three delaydevices 204 a, 204 b, and 204 c. Circuit 200 can be used in lieu of LFSR104 of circuit 100 to generate the code words of a (7, 4) CRC code.

Circuit 200 generates a group of CRC bits or a CRC codeword (R₃, R₂,R₁), wherein R₁ is output from delay device 204 a, R₂ is output fromdelay device 204 b, and R₃ is output from delay device 204 c. Theiteration bound (settling time) of circuit 200 is equal to the settlingtime of two adders 202 (i.e., 2T_(adder)). This is due, for example, tothe fact that the output of adder 202 b is dependent on the output ofadder 202 a. Circuit 200 operates in a manner similar to that of circuit100 except that two information bits are provided to circuit 200, ratherthan the one information of circuit 100, during each clock cycle ofcircuit 200.

In order to better understand the operation of circuit 200, consider thefollowing example wherein circuit 200 is used to generate a CRC codewordfor a group of four information signal bits (1, 1, 0, 1). These are thesame four information signal bits used above to illustrate the operationof LFSR 104.

Initially, each of the outputs of the delay devices 204 is a 0 bit(i.e., the codeword (R₃, R₂, R₁) of circuit 200 is (0, 0, 0) before thefirst of four information signal bits (1, 1, 0, 1) is provided tocircuit 200). During a first clock cycle of circuit 200, the first bitof the four bits (1) is provided to adder 202 a and the second bit ofthe four bits (1) is provided to adder 202 d. The input to adder 202 ais referred to as input B₀. The 0 output bit of delay device 204 a isadded to this first information signal bit (i.e., 1), using modulus-2addition, to form an output bit equal to one (0+1=1). This output bit(1) is then provided as an input to both adder 202 b and adder 202 c. Asa result, the output of adder 202 b becomes 1 (0+1=1).

During this same clock period, the second bit of the information signal(1) is provided as an input to adder 202 d. This input to circuit 200 isreferred to as input B₁. The output of delay device 204 b is then addedto this second information signal bit (i.e., 1) to form an output bitequal to 1 (0+1=1). This output bit is provided as an input bit to adder202 c and delay device 204 c. As a result, adder 202 c forms an outputbit equal to 0 (1+1=0). At the start of the next clock cycle, clockcycle two, the outputs of each of the delay devices 204 are changed tothat of their inputs, and the codeword (R₃, R₂, R₁) of circuit 200 ischanged from (0, 0, 0) to (1, 0, 1).

During the second clock cycle of circuit 200, the third bit of the fourinformation bits (0) is provided to adder 202 a. The 1 output bit ofdelay device 204 a is added to this third information signal bit (i.e.,3) to form an output bit equal to one (1+0=1). This output bit (1) isthen provided as an input to both adder 202 b and adder 202 c. As aresult, the output of adder 202 b becomes 0 (1+1=0). During this sameclock period, the fourth bit of the information signal (1) is providedas an input to adder 202 d. The output of delay device 204 b is thenadded to this fourth information signal bit (i.e., 1) to form an outputbit equal to 1(0+1=1). This output bit is provided as an input bit toadder 202 c and delay device 204 c. As a result, adder 202 c forms anoutput bit equal to 0 (1+1=0). At the start of the next clock cycle,clock cycle three, the outputs of each of the delay devices 204 ischanged to that of their inputs, and the codeword (R₃, R₂, R₁) ofcircuit 200 is changed from (1, 0, 1) to (1, 0, 0). This is summarizedbelow in Table 2.

TABLE 2 Output Bits Delay Delay Delay CLK Input Bits Device DeviceDevice Cycle Input B₀ Input B₁ 204c 204b 204a 1 1 1 0 0 0 2 0 1 1 0 1 10 0

As can be seen from the above example, circuit 200 generates the samecodeword in two clock cycles as LFSR 104 generates in four clock cycles.The CRC code words generated by circuit 200 are appended to fourinformation signal bits for transmission in a manner similar to thatdescribed above with regard to circuit 100.

Theoretically, the circuit of FIG. 1 can be further unfolded in anattempt to further reduce processing time. As illustrated by the circuitof FIG. 3, however, further unfolding using conventional unfoldingtechniques can lead to increased circuit settling times and/or aninability to generate desired results.

FIG. 3 is a block diagram of a three parallel paths circuit 300 obtainedby unfolding the LFSR 104 of circuit 100. As shown in FIG. 3, circuit300 has six adders 302 a, 302 b, 302 c, 302 d, 302 e, and 302 f andthree delay devices 304 a, 304 b, and 304 c. Circuit 300 operates in amanner similar to that described above for circuit 200, and generatesthe codeword in two cycles. However, due to the increased unfolding, thesetting time of the circuit is now equal to the settling time of fouradders 302 (i.e., 4T_(adder)), which is double the setting time ofcircuit 200. This can be seen by noting that the output of adder 302 cis dependent on the outputs of adders 302 a, 302 f, and 302 e. Thislimitation of conventional unfolding, however, is overcome by thepresent invention as illustrated by the circuits of FIG. 4 and FIG. 5

FIG. 4 is a block diagram of a circuit 400 obtained by adding anadditional time delay to the innermost nested feedback loop of thecircuit 100 in accordance with the invention. Adding one or moreadditional time delays to the innermost nested feedback loop of acircuit prior to unfolding is a technique of the present invention.Typically, the number of time delays added to the innermost nestedfeedback loop of a circuit is selected to make the total number of timedelays in the innermost nested feedback loop divisible by a desiredunfolding factor. For example, a circuit that is to be unfolded by afactor of three would typically have 3, 6, 9, etc., time delays. Thistechnique of the invention is further described below. Adding one ormore additional delays to the innermost nested feedback loop of acircuit prior to circuit unfolding allows the present invention toovercome the increased circuit settling time limitations associated withconventional unfolding techniques.

Circuit 400 includes a switch 402 and a linear feedback shift register(LFSR) 404. Switch 402 has three ports (a, b, and c). LFSR 404 has fourdelay devices 406 a, 406 b, 406 c, and 406 d. LFSR 404 also has twoadders 408 a and 408 b. The innermost nested feedback loop of LFSR 404is formed by adder 408 a, adder 408 b, delay devices 406 c, 406 b and406 a, and the conductors coupling these devices together.

Circuit 400 operates in a manner similar to that described above forcircuit 100. Circuit 400 can be represented by a polynomial P(x)=1+X+X⁴.P(x) has two high-order leading-zero term (i.e., the X² and the X³ termsare equal to zero).

The settling time of circuit 400 before unfolding is equal to thesettling time of two adders 408 (i.e., ²T_(adder)). This can be seen bynoting that the output of adder 408 b is dependent on the output ofadder 408 a.

FIG. 5 is a block diagram of a three parallel paths circuit 500 obtainedby unfolding the LFSR 404 of circuit 400 in accordance with theinvention. As shown in FIG. 5, circuit 500 has six adders 502 a, 502 b,502 c, 502 d, 502 e, and 502 f and four delay devices 504 a, 504 b, 504c, and 504 d.

Circuit 500 is similar to that described above for circuit 300. However,the settling time of circuit 500 is equal to the settling time of twoadders 502 (i.e., 2T_(adder)), which is the same as the setting time ofcircuit 400. Thus, as illustrated by FIG. 5, the unfolding technique ofthe invention overcomes the limitations of conventional unfoldingtechniques.

The unfolding technique of the invention is not limited by the examplecircuits illustrated herein. For example, two additional time delays canbe added to the innermost nested feedback loop of LFSR 104 such thateach delay device 106 a and 106 b is effectively a 2T delay device. Inthis instance, if LFSR 104 is unfolded to form two parallel paths, eachof the delay devices 204 a and 204 b in circuit 200 would become a 2Tdelay device. In embodiments of the invention additional time delays areadded to the innermost nested feedback loop of LFSR 104 to permitincreased unfolding in accordance with the invention and therebyincrease the rate at which cyclic code words can be generated.

As illustrated by FIG. 6A, FIG. 6B, and FIG. 7, the techniques of thepresent invention described above are used to form encoders forgenerating cyclic codes that are capable of operating at high datarates.

FIG. 6A is a block diagram of an example encoder 600 according to theinvention for generating the code words of a (7, 4) CRC code. Encoder600 includes a first transform circuit 602, a LFSR 604, a secondtransform circuit 606 (which is another LFSR circuit), and a switch 608.Encoder 600 is different from circuit 100 in that it includes twotransform circuits in addition to the LFSR 604, and LFSR 604 implementsa different generator polynomial than LFSR 104. As described above, LFSR104 implements the generator polynomial G(x) equals (1+X+X³). LFSR 604,however, implements the generator polynomial G₂(x) equals (1+X+X²+X⁵).G₂(x) has two high-order leading-zero terms (i.e., the X³ and X⁴ termsare equal to zero). The generator polynomial G₂(x) is obtained bymultiplying the generator polynomial G(x) equals (1+X+X³) by thepolynomial G₁(x) equals (1+X).

As will be understood by a person skilled in the relevant arts given thedescription herein, transform circuit 602 adds, using modulus-2addition, the bits of a digital input signal U(x) to a copy of thedigital input signal U(x) delayed by two time delays. This is equivalentto multiplying the bits of the digital input signal U(x) by thepolynomial G₁(x) equals (1+X²). Transform circuit 602 includes an adder612 a and two delay devices 610 a and 610 b. The output of transformcircuit 602 is a transformed information signal, T(x).

The devices of LFSR 604 operate in a manner similar to the devicesdescribed above with regard to LFSR 104. LFSR 604 implements a divisionoperation and generates remained bits R₁(x) at the output of a delaydevice 610 c. These remainder bits are used to form a (7, 4) CRC code.LFSR 604 includes, in addition to delay device 610 c, delay devices 610d, 610 e, 610 f, and 610 g, and three adders 612 b, 612 c, and 612 d.LFSR 604 divides the bits of the transformed information signal T(x) byG₂(x), wherein G₂(x) equals G(x)G₁(x). In embodiments of the invention,LFSR 604 is unfolded according to the invention to form three parallelprocessing paths and thereby increase the rate at which encoder 600processes data.

Transform circuit 606 transforms the remainder bits generated by LFSR604 into the (7, 4) CRC code words generated by circuit 100. Transformcircuit 606 adds the output signal generated at the output of delaydevice 610 c by a delayed copy of this output signal. The delayed copyof the output signal is delayed by two time delays. Transform circuit606 is equivalent to computing the quotient obtained by dividing theremainder bits generated by LFSR 604 by the polynomial G₁(x) equals(1+X²).

Switch 608 operates similarly to switch 102 of circuit 100. Switch 608can be any conventional electronic switch such as, for example, anyconventional type of field effect transistors (FET).

FIG. 6B is a block diagram of an example three parallel paths circuit650 according to the invention. Circuit 650 is obtained by unfoldingcircuit 600 by a factor of three.

As shown in FIG. 6B, first transform circuit 602, LFSR 604, and secondtransform circuit 606 (which is another LFSR circuit) have each beenunfolded in accordance with the invention. The unfolded first transformcircuit 602 includes two delay devices 610 and three adders 612. Theunfolded LFSR 604 includes five delay devices 610 and nine adders 612.The unfolded second transform circuit 606 includes two delay devices 610and three adders 612.

FIG. 7 illustrates a simplified schematic of a second encoder 700 forgenerating a cyclic code according to an embodiment of the invention.Encoder 700 includes a transform circuit 702, a first LFSR 704, a secondLFSR 706 and two modulo-2 adders 708 a and 708 b. The purpose oftransform circuit 702 is to transform the bits of an information signalU(x) into the bits of a transformed information signal T(x). LFSR 704implements a generator polynomial G₂(x) formed by multiplying aconventional generator polynomial G(x) for implementing a particularcyclic code by a polynomial G₁(x). As described herein, the polynomialG₁(x) is selected to increase the number of delays formed in theinnermost nested feedback loop of LFSR 704. As described above, LFSR 704may be unfolded/reformulated in accordance with the invention so as toavoid increasing the settling time (loop bound) of theunfolded/reformulated circuit. LFSR 706 implements a small degreepolynomial used to transform the remained bits (code words) generated byLFSR 704 into the code words of a desired cyclic code (i.e., the codewords that would typically be generated by the particular generatorpolynomial G(x) that was multiplied by the polynomial G₁(x)). How toimplement encoder 700 will become apparent to persons skilled in therelevant arts given the description of the invention herein.

FIG. 8 is a block diagram of a second example LFSR circuit 800 forgenerating a cyclic code. This circuit can be derived from a circuitsimilar to circuit 100 (see FIG. 1) by retiming. Circuit 800 is used togenerate the code words of a BCH code. As described below, the operationof circuit 800 is similar to the operation of circuit 100.

FIG. 8 is provided as a second example circuit that can serve as a basisfor making an encoder according to the invention. Other circuits forgenerating cyclic codes that can serve as a basis for making an encoderaccording to the invention will be known to persons skilled in therelevant arts given the description herein.

As shown in FIG. 8, circuit 800 includes three switches 802 a, 802 b and802 c, and an LFSR 804. LFSR 804 includes several delay devices 806 andseveral adders 808. Switch 802 a has two ports (a and b). Switches 802 band 802 c have three ports (a, b, and c). Switches 802 can be anyconventional electronic switches such as, for example, any conventionaltype of field effect transistors (FET). Delay devices 806 can be anyconventional type of delay devices such as, for example, D-flipflops.Similarly, adders 808 can be any conventional type of modulo-2 addercircuits. As can be seen in FIG. 8, LFSR 804 has several nested feedbackloops. Delay device 806 a forms a part of all of the nested feedbackloops of LFSR 804.

Similar to circuit 100, circuit 800 has two operating modes. In a firstoperating mode, a BCH codeword is generated by LFSR 804. In a secondoperating mode, the generated BCH codeword is shifted out of LFSR 804.

In the first operating mode of circuit 800, the a-ports of switches 802a, 802 b, and 802 c are electrically coupled to the b-ports. As usedherein, two devices or nodes of a circuit are electrically coupled if asignal at one device or node of the circuit can be sensed at anotherdevice or node of the circuit. The sensed signal may be stored,filtered, and/or amplified, for example, before being sensed at anotherdevice or node of the circuit. In this first mode, bits of a digitalinformation signal are input to the a-port of switch 802 a. During eachclock cycle of circuit 800, a bit of the digital information signal isoutput at the b-port of switch 802 b. This same bit is also provided toadder 808 a. The bit provided to adder 808 a is added to an output ofdelay device 806 a to form a resultant bit. This resultant bit is thenprovided as an input to each of the other adders 808 (e.g., adders 808b, 808 c, and 808 d) of LFSR 804 and to delay device 806 d of LFSR 804.How LFSR loop 804 operates to generate a BCH codeword given a group ofinformation signal bits would be known to a person skilled in therelevant arts given the description herein. The bits of the generatedcodeword are the outputs of each of the delay devices 806.

In the second operating mode of circuit 800, the a-ports of switches 802a, 802 b, and 802 c are not electrically coupled to the b-ports. In thissecond mode, the c-port of switch 802 b is electrically coupled to theb-port of switch 802 b. Since the a-port of switch 802 c is notelectrically coupled to the b-port, the output of adder 808 a is not fedback to any adder 808 or any delay device 806 of LFSR 804. In thissecond mode, during each clock cycle of circuit 800, a bit of thegenerated codeword is output at the b-port of switch 802 b. By switchingbetween the two modes of operation, circuit 800 generates code words andappends these code words to groups of bits of an information signal.

As described herein, the invention can be applied to circuit 800 to forma BCH encoder in a manner similar to that described above for circuit100. A person skilled in the relevant arts given the description hereinwill be able to apply the invention to circuit 800 in order to make anduse a BCH encoder according to the invention. In an embodiment, a BCHencoder according to the invention has the form of encoder 700 describedabove.

FIG. 9 and FIG. 10 illustrate how to apply the invention to retimedcircuits. FIG. 9 illustrates an example embodiment of a LFSR circuit 900that is equivalent to circuit 400 of FIG. 4. Circuit 900 is obtained byretiming circuit 400. FIG. 10 illustrates an example circuit 1000according to the invention. Circuit 1000 is obtained by unfoldingcircuit 900 by a factor of three in accordance with the invention.Circuit 1000 illustrates how to apply the invention to retimed circuitssuch as, for example, the CRC circuits illustrated by FIG. 1 and FIG. 4.

Example Method for Generating Cyclic Codes According to the Invention

In this section, an example method for generating cyclic codes accordingto the invention is described. This method can be implemented using thetechniques and circuit embodiments of the invention described above. Theexample method is not limited, however, to being implemented using onlythe circuits described herein.

FIG. 11 is a flowchart of the steps of a method 100 for generatingcyclic codes for error control in digital communications. In the exampleof FIG. 11, method 1100 includes four steps 1102, 1104, 1106, and 1108.Method 1100 starts with step 1102.

In step 1102, a K-bit information signal is received. This informationsignal is represented by a polynomial U(x) having a degree K−1.

In step 1104, the information signal U(x) is transformed to form atransformed information signal. The information signal U(x) istransformed using a first transform represented by a polynomial G₁(x)having a degree P. P is greater than zero. The transformed informationsignal is represented by a polynomial T(x) having a degree K+P−1. T(x)equals U(x)G₁(x).

In an embodiment, step 1104 involves adding the information signal U(x),using modulo-2 addition, to at least one time-shifted copy of theinformation signal to form the transformed information signal T(x).

In an embodiment, step 1104 can be implemented, for example, using thetransform circuit 702 of circuit 700.

In step 1106, an initial cyclic code is generated for the transformedinformation signal T(x) using a second transform represented by apolynomial G₂(x). This initial cyclic code is represented by apolynomial R₁(x). G₂(x) has high-order leading-zero terms. R₁(x) equalsthe remainder obtained by dividing T(x) by G₂(x).

In one embodiment, the K bits of the information signal U(x) are dividedinto at least two subsets of bits. These at least two subsets of bitsare processed in parallel to generate the initial cyclic code R₁(x).

In an embodiment, step 1106 can be implemented, for example, using theLFSR 704 of circuit 700. As described herein, in embodiments, circuit700 is unfolded in accordance with the invention to increase the rate atwhich data is processed.

In step 1108, the initial cyclic code R₁(x) is transformed to form afinal cyclic code represented by a polynomial R₂(x). The initial cycliccode R₁(x) is transformed using the first transform G₁(x). R₂(x) equalsR₁(x)G₁(x).

In one embodiment, the final cyclic code formed is a cyclic redundancycheck code. In another embodiment, the final cyclic code formed is aBose-Chaudhuri-Hocquenghem code. In a further embodiment, the finalcyclic code formed is a Reed-Solomon code. Other cyclic codes are alsopossible in accordance with the invention.

In an embodiment, step 1108 can be implemented, for example, using theLFSR 706 of circuit 700.

Given the description herein, a person skilled in the relevant arts willunderstand how to implement each of the steps of method 100 to generatea desired cyclic code capable of operating as a part of a high speeddigital communications system.

CONCLUSION

Various embodiments of the present invention have been described above.It should be understood these embodiments have been presented by way ofexample only, and not limitation. It will be understood by those skilledin the relevant arts that various changes in form and details of theembodiments described above may be made without departing from thespirit and scope of the present invention as defined in the claims.Thus, the breadth and scope of the present invention should not belimited by any of the above-described exemplary embodiments, but shouldbe defined only in accordance with the following claims and theirequivalents.

1. A system for generating cyclic codes for error control in digitalcommunications, comprising: a circuit that receives a K-bit informationsignal represented by a polynomial U(x) having a degree K−1; a circuitthat transforms the information signal to form a transformed informationsignal, using a first transform represented by a polynomial G₁(x) havinga degree P, wherein P is greater than zero, the transformed informationsignal is represented by a polynomial T(x) having a degree K+P−1, andT(x) equals U(x)G₁(x); a circuit that generates an initial cyclic coderepresented by a polynomial R₁(x) for the transformed information signalusing a second transform represented by a polynomial G₂(x), whereinR₁(x) equals a remainder obtained by dividing T(x) by G₂(x); and acircuit that transforms the initial cyclic code to form a final cycliccode represented by a polynomial R₂(x) using the first transform,wherein R₁(x) equals R₁(x)/G₁(x).
 2. The system of claim 1, wherein saidcircuit that transforms the information signal to form the transformedinformation signal includes digital logic that adds the informationsignal to at least one time-shifted copy of the information signal. 3.The system of claim 1, wherein said circuit that generates the initialcyclic code comprises a linear feedback shift register.
 4. The system ofclaim 1, wherein said circuit that transforms the initial cyclic codecomprises a linear feedback shift register.
 5. The system of claim 1,wherein the K bits of the information signal are processed in parallelto generate the initial cyclic code.
 6. The system of claim 1, whereinthe final cyclic code is a cyclic redundancy check code.
 7. The systemof claim 1, wherein the final cyclic code is aBose-Chaudhuri-Hocquenghem code.
 8. The system of claim 1, wherein thefinal cyclic code is a Reed-Solomon code.
 9. A system for generatingcyclic codes for error control in digital communications, comprising:means for receiving a K-bit information signal represented by apolynomial U(x) having a degree K−1; means for transforming theinformation signal to form a transformed information signal, using afirst transform represented by a polynomial G₁(x) having a degree P,wherein P is greater than zero, the transformed information signal isrepresented by a polynomial T(x) having a degree K+P−1, and T(x) equalsU(x)G₁(x); means for generating an initial cyclic code represented by apolynomial R₁(x) for the transformed information signal using a secondtransform represented by a polynomial G₂(x), wherein R₁(x) equals aremainder obtained by dividing T(x) by G₂(x); and means for transformingthe initial cyclic code to form a final cyclic code represented by apolynomial R₂(x) using the first transform, wherein R₂(x) equalsR₁(x)/G₁(x).
 10. The system of claim 9, wherein said means fortransforming the information signal to form the transformed informationsignal includes means for adding the information signal to at least onetime-shifted copy of the information signal.
 11. The system of claim 9,wherein said means for generating the initial cyclic code comprises alinear feedback shift register.
 12. The system of claim 9, wherein saidmeans for transforming the initial cyclic code comprises a linearfeedback shift register.
 13. The system of claim 9, further comprising:means for processing the K bits of the information signal in parallel togenerate the initial cyclic code.
 14. The system of claim 9, wherein thefinal cyclic code is a cyclic redundancy check code.
 15. The system ofclaim 9, wherein the final cyclic code is a Bose-Chaudhuri-Hocquenghemcode.
 16. The system of claim 9, wherein the final cyclic code is aReed-Solomon code.
 17. A method for generating cyclic codes for errorcontrol in digital communications, comprising (1) receiving a K-bitinformation signal represented by a polynomial U(x) having a degree K−1;(2) transforming the information signal to form a transformedinformation signal, using a first transform represented by a polynomialG₁(x) having a degree P, wherein P is greater than zero, the transformedinformation signal is represented by a polynomial T(x) having a degreeK+P−1, and T(x) equals U(x)G₁(x); (3) generating an initial cyclic coderepresented by a polynomial R₁(x) for the transformed information signalusing a second transform represented by a polynomial G₂(x), whereinR₁(x) equals a remainder obtained by dividing T(x) by G₂(x); and (4)transforming the initial cyclic code to form a final cyclic coderepresented by a polynomial R₂(x) using the first transform, whereinR₂(x) equals R₁(x)/G₁(x).
 18. The method of claim 17, wherein step (2)comprises: adding the information signal to at least one time-shiftedcopy of the information signal to form the transformed informationsignal.
 19. The method of claim 17, wherein step (3) comprises: dividingthe K bits of the information signal into at least two subsets of bits;and processing the at least two subsets of bits in parallel to generatethe initial cyclic code.
 20. The method of claim 17, wherein step (4)comprises: forming a cyclic redundancy check code.
 21. The method ofclaim 17, wherein step (4) comprises: forming aBose-Chaudhuri-Hocquenghem code.
 22. The method of claim 17, whereinstep (4) comprises: forming a Reed-Solomon code.